1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device, in particular, to a method of manufacturing a semiconductor device characterized by a method of forming a bump electrode on an opening of a semiconductor substrate.
2. Description of the Related Art
In order to utilize a main surface of a semiconductor substrate effectively, a technique of forming a bonding electrode for electric connection with an external board or the like on a back surface of a semiconductor die has been introduced. For this technique, a technique of forming a bump electrode 28 made of solder or the like on an electrode formed on a back surface has been prevailingly used as a CSP technique has been developed. Hereafter, a method of forming this bump electrode 28 will be described referring to FIGS. 5A and 5B. First, as shown in FIG. 5A, a first wiring 23 is formed on a main surface of a semiconductor substrate 21 with a first insulation film 22 made of an oxide film or the like being interposed therebetween. An opening 24 is then formed in the semiconductor substrate 21 from the back surface of the semiconductor substrate 21 so as to expose the back surface of the first wiring 23.
Then a second insulation film 25 made of an oxide film or the like is formed in the opening 24 and on the back surface of the semiconductor substrate 21, the back surface of the first wiring 23 is then exposed, and a second wiring 26 is formed from inside the opening 24 onto the back surface so as to be connected to the back surface of the wiring 23. Finally, a solder paste or the like is printed in a region on the back surface including the opening 24 by a screen printing method or the like to form a solder layer 27, and the solder layer 27 is reflowed to form the bump electrode 28 connected to the first wiring 23 as shown in FIG. 5B. A protection film 30 is formed on the first wiring 23.
This kind of technique such that the bump electrode 28 made of solder or the like is formed on the back surface of the semiconductor substrate 21 is described in Japanese Patent Application Publication No. 2007-165696.
Conventionally, as described above, the solder layer 27 made of a solder paste or the like is formed thick on the back surface of the semiconductor substrate 21 so as to cover the opening 24 in which the second wiring 26 connected to the first wiring 23 is formed. Since gas 31 trapped and remaining between the solder paste or the like and the opening 24 may form a void 29 after the reflowing process, various attempts have been made to prevent the void 29, such as performing a defoaming treatment while forming the solder layer 27. As other attempt, the bump electrode 28 is formed away from the opening 24 in order to prevent this problem and the increase of the processes. If these attempts are not made and the void 29 is formed, the void 29 repeats expansion and contraction by a subsequent heat treatment cycle for mounting the semiconductor substrate 21 on a mounting board and by the heat of the semiconductor device 21 or the like during the use after the mounting, thereby causing a problem such as cracking at this portion. Furthermore, impurities from the solder paste or the like that remain in the void 29 may corrode the bump electrode 28 or the like. Accordingly, it is necessary to solve these problems by preventing the void 29 from being formed in the bump electrode 28 without an additional process such as a defoaming treatment or the like.